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*            Team Thrasher's awesome HC11 program    
*
*                    Version 0.5, thu. 3:20am
*
*       includes code for but does not implement the bias scheme
*       (holding on the bias until the D/A converter is finished)
*      
*       attempts to include a delay, so that the HC11 outputs the
*       current value and waits until the next sample is ready
**            basically, set the value of WAIT to the number
**            loop executions that gives the delay you want;
**            then decrement that value until it's zero, i.e.
**            the loop has been executed that many times.
**            NOTE: set WAIT to n+1 since the first 
**                  thing the loop does is decrement!
*          (another option here is to use the HC11's clock speed 
*           as the sampling time and implement no waiting, only
*           constant sample-and-operate...)
*
*       try to work around MUL's unsigned property by using repeated 
*       addition to do integer multiplications (A/D section)...  since 
*       this is still multiplication, it needs 16-bit registers!
*
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*   EQUs and variable initializations

      PORTB   EQU     $1004   output port
      ADR1    EQU     $31     1st A/D result register
      ADR2    EQU     $32     2nd A/D result register
      ADR3    EQU     $33     3rd A/D result register
      ADR4    EQU     $34     4th A/D result register

      ZERO    EQU     $40
      ZERO    RMB     0       define the value 0 to use in clearing registers

                           *************
      GAINK   RMB  2       set value of compensator gain!!!!
                           *************
**      BIAS    RMB  4       set value of output bias

      WAIT    RMB  101	 this is the number of loops plus one to 
                         * wait in the hold loop (near the end)

***********************************************
* start the program proper
*    **** what's the proper ORG address ???!?!?!?!  *****

       ORG     $40

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*  PART ONE: Reading and summing of input data

*      this requires loading the 8-bit inputs from ADR1-ADR4 into the 
*      lower half of the 16-bit double accumulator, and making a 16-bit 
*      integer of it. normally this means filling the upper bits with 
*      the MSB of the lower half, i.e. filling A with B7, since B7 is 
*      the sign bit.... however, the raw data from the detectors and 
*      partial summers will be positive ONLY.  thus the upper half must 
*      be all zeroes!  Clear A by loading it with the the value zero.


start  NOP
       ** first input (positive outer channel):  gain = 2
       LDB    ADR1         load ADR1  -- 8-bit -- into B (lower half of D)
       LDA    ZERO         make 8-bit value 16-bits long
       STD    SUM          store in SUM  --- sum = ADR1
       ADDD   SUM          add SUM and D --- sum = sum+ADR1 = ADR1+ADR1 = 2*ADR1
       STD    SUM          store in SUM
       ** second input (positive partial sum): gain = 1
       LDB    ADR2         load ADR2  -- 8-bit -- into B
       LDA    ZERO         make 8-bit value 16-bits long
       ADDD   SUM          add SUM and D ---  sum = sum+ADR2 = 2*ADR1+ADR2
       STD    SUM          store in SUM
       ** third input (negative partial sum): gain = -1
       LDB     ADR3        load ADR3  -- 8-bit -- into B
       LDA     ZERO        make 8-bit value 16-bits long
       STD     THREE       store in THREE  -- THREE = ADR3
       LDD     SUM         load SUM into D 
       SUBD    THREE       subtract THREE from SUM
       ** fourth input (negative outer channel): gain = -2
       LDB     ADR4        load ADR4  -- 8-bit -- into B
       LDA     ZERO        make 8-bit value 16-bits long
       STD     FOUR        store in FOUR  --- four = ADR4
       ADDD    FOUR        add FOUR and D --- four = ADR4+ADR4
       STD     FOUR        store in FOUR
       LDD     SUM         load SUM into D
       SUBD    FOUR        subtract FOUR from SUM


********************************************
*  PART TWO: implementation of the compensator

       LDA     GAINK    put main gain value into A
                        *** lower half of SUM is still in B!!!
       MUL              AxB->D 
**       ADDB    BIAS     BIAS + B --> B  -- add in output bias
       STB     PORTB    write B (8-bit signal) to output port

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**  PART THREE:  waiting for the next sampling period

      LDX     WAIT     load (desired number)+1 of hold loops
hold  DEX              count down one
      BNE     hold     if not zero, keep going

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**     then restart the main loop

       BRA     start   branch to label start

       END